1. Field of the Invention
The present invention relates to a method of and circuitry for staggering the refresh signals to a dynamic random access memory (DRAM) to avoid large power supply current spikes while simultaneously minimizing the effect on memory access bandwidth.
2. Discussion of the Prior Art
The memory cells of a dynamic RAM (DRAM) are, basically, charged storage capacitors with driver transistors. The presence or absence of charge in a particular memory cell capacitor is interpreted by the DRAM's sense line as a logical 1 or 0. However, because of the natural tendency of the charge in the cell to distribute itself into a lower energy-state configuration, DRAM cells require periodic charge "refreshing" to maintain stored data.
This refresh requirement means that additional DRAM control circuitry must be implemented. Since the refresh procedures make the DRAM unavailable for writing or reading during the refresh cycles, memory control circuitry is required to arbitrate memory access. Furthermore, as shown in FIG. 1, in large DRAM arrays, the conventional method of refreshing all DRAM banks at the same time can cause severe power supply glitches.
Referring to FIG. 2, one obvious method for solving the large current spike problem associated with simultaneous refresh is to refresh sequentially, i.e., one DRAM bank at a time. This requires, however, in the case of four DRAM banks as illustrated in FIG. 2, that four refresh cycles be performed every 16 .mu.sec., the maximum allowable time between refresh cycles in order to refresh every row in the DRAM within the required amount of time. Since each refresh typically requires 400 nsec. to complete (at 10 MHz), sequential refresh requires 4.times.400 nsec., or 1.6 .mu.sec., each 16 microseconds in order to refresh all banks. Thus, refresh is being performed 10% of the time, seriously decreasing memory access bandwidth.